If you dig long enough, you eventually find what you need in the documentation. When I do IC layout, I do most of my work on the lower metals, M1-M3, and then I glue them together with higher metals. I realized that I did not have M3-M4 in the via menu, which makes me very nervous because it made me wonder if I had the wrong settings on my PDK for CMRF8SF.
The answer resided in the cdslib release notes, and I failed to see it when I installed the kit months ago.
"If a design library is created and attached to cmrf8sf as the reference library, note that the cmrf8sf library has been compiled for 3-2 in LM and DM (4-2 in OL, 5-1 in AM) designs. If your location requires a different metallization, the library may be recompiled using the ASCII technology files by the library administrator."
Here's the kicker, you need access to the file, "Design Kit and Technology Training CMOS8RF", to get an explanation; however, I happen to know how to do this.
From the Cadence CIW, select Tools->Technology File Manager->Load. The "Load Technology File" window will appear.
2. Specify the following: ASCII Technology File: IBM_PDK/cmrf8sf/relDM/cdslib/cmrf8sf/techfile*.asc (the dialog defaults to *.tf, so select all file types)
Classes: Choose Select All. This will load all the classes or objects in the techfile.
Mode: Select Replace.
This will make a new tech.db file in the directory, and then you should be ready to go.
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