Thursday, April 30, 2015

CMRF8SF: Resistor device mismatch, the saga continues, and the fix.

Previously, I mentioned that I was having issues with resistor extraction mismatch. I had some success that ended suddenly, and it forced me to carefully look at the kit. You need to preprocess your netlists in the schematic. The kit uses the file "cdl_processor.pl" to convert the extraction from the schematic.

The LVS release notes:
Hierachical LVS has requirements for CDL netlist inputs which require changes in the standard output of CDL. Because of these requirements, a CDL processing program is included within the IBM design kit.

In your schematic:
IBM_PDK->Netlist->CDL
IBM_PDK->Netlist->CDL Processor for LVS
This creates a file called (schematic).netlist.lvs.
In Calibre LVS (nmLVS) under Inputs, selected the "Netlist" tab and uncheck "export from schematic viewer" and specify the spice file as (schematic).netlist.lvs

CMRF8SF: bondpad bad device

It took me 3 weeks to completely port a FPGA from cmos14soi to cmrf8sf, so let's say that I generally know what I'm doing in the world of VLSI layout. I have always found that the padframes take the longest of any component to DRC/LVS clean, and this is the single most under-estimated component. Part of this is my fault as I optimize my padframe and pads for different performance because I'm stuck with a few packages. If you are getting strange "bad device" errors in your bondpad cell, make sure that the M1 at the bondpad edge is connected by a contiguous ring of "BFMOAT IND". My corner cells causes a whole padframe to not LVS. 2 days to figure that out.

Tuesday, April 28, 2015

CMRF8SF: resistor device mismatch

I use a single resistor in my padframe for my floating-gate tunneling voltage.
It did not extract. Even if I had a cell with only the resistor, it would fail Calibre LVS. After a bunch of trial and error, I realized that it must be something that is just crazy. I tried to LVS with ic6.1.4 and it worked! It seems that resistor LVS works with every version of Cadence but 6.1.5.

Friday, April 24, 2015

CMRF8SF, wrong metals but not really, so recompile the techfile

If you dig long enough, you eventually find what you need in the documentation. When I do IC layout, I do most of my work on the lower metals, M1-M3, and then I glue them together with higher metals. I realized that I did not have M3-M4 in the via menu, which makes me very nervous because it made me wonder if I had the wrong settings on my PDK for CMRF8SF.

The answer resided in the cdslib release notes, and I failed to see it when I installed the kit months ago.
"If a design library is created and attached to cmrf8sf as the reference library, note that the cmrf8sf library has been compiled for 3-2 in LM and DM (4-2 in OL, 5-1 in AM) designs. If your location requires a different metallization, the library may be recompiled using the ASCII technology files by the library administrator."

Here's the kicker, you need access to the file, "Design Kit and Technology Training CMOS8RF", to get an explanation; however, I happen to know how to do this.

From the Cadence CIW, select Tools->Technology File Manager->Load. The "Load Technology File" window will appear.
2. Specify the following: ASCII Technology File: IBM_PDK/cmrf8sf/relDM/cdslib/cmrf8sf/techfile*.asc (the dialog defaults to *.tf, so select all file types)
Classes: Choose Select All. This will load all the classes or objects in the techfile.
Mode: Select Replace.
This will make a new tech.db file in the directory, and then you should be ready to go.

CMRF8SF, it's always that last metal: 4-1-3

130nm 8RF DM is 4thin-1thick-3rf (M1-M4,MQ,LY,E1,MA)
No one ever spells out the metal order in the design manuals.
My SKILL scrips had an error, which is now fixed, but you'd think that it'd be easier to find metal stacks.

Saturday, April 11, 2015

Cadence and Virtuoso, versions get me.

If you are accustomed to use icadv12, and then you use a kit that needs ic6, make sure that you realize that they aren't compatible. IC12 didn't throw any warnings on the 8sf kit, but it generated some serious nastiness. I am so used to using IC12, I just didn't think to consider that the older design kit would need an older tool set.

Anyone want to give a few million to make a quality competitor for schematic and layout?

A new calendar system: Ivy Mike

I have a real issue with dating items. The biggest issue is the non-uniform formats. I got an email today that said they needed something by 08/07/2015. What does that mean? August? July? This is why I personally use the format of 08 JUL 2015.
But 2015, that is pretty arbitrary too. I could use the Islamic Calendar or the Japanese Calendar; however, I think a better way is to use something that will be relevant in 1000 years: Ivy Mike Calendar
That makes this year to be "63 IM", and the date of this post, in a usable format, 11 APR 63IM.

Thursday, April 9, 2015

Assessing Trends in Performance per Watt for Signal Processing Applications

Now that my latest paper has been accepted, Assessing Trends in Performance per Watt for Signal Processing Applications, I can actually talk about the what was important about it. This paper is about power, so here are the important parts:
  • Processing GMAC/W calculations are approaching a Powerwall
  • Memory Power halves every 29 years, which creates a fixed power requirement
  • Non-data flow: Cache is king
The summary is that data-flow processing will have stagnant power improvements from scaling, memory transfers are of fixed power, and cache is really not helping as much as you think when it comes to relative performance per Watt.

The GMAC, everybody does it.

The Multiply ACcumulate (MAC) is a mathematical calculation that computers spend a good deal of their time doing. It's used heavily in natural signal processing, such as audio, and video cards have GPUs that designed to quickly do these calculations. There are two players in the marketing of the semiconductor space who have "Law's" that are not actual laws, but more of trends that have been noticed: Moore and Koomey[1]. Moore said that more transistors will fit on a die, and Koomey did a survey that showed that power consumption is still scaling. The assumption is that as transistors have scaled, their relative behavior has scaled, which is not true. Another item that comes into to play on the marketing side is how you measure power. Most processors offload some power requirements to RAM that has sense amps just burning current to have an effective input capacitance, which makes the CPU power lower at the cost of increased RAM power. If you really want to get a good feel for the power requirements of a system the Giga-MAC per Watt (GMAC/W) is a great calculation.

The the graph above, I present Koomey's system trend and then the trend specific to the GMAC/W . Koomey included systems until 2006, but did not focus on specifically on data flow applications. If you are trying to do things like audio, video games, watching the sky, processing speech, RADAR, and just about any natural system, you are burdened by how much data you can move through the system, and how to get the heat out and data and power in. I am confident that for digital approaches there exists a Powerwall at between 10 to 30 GMAC/W. ie: the end of useful scaling for power constrained systems.

When I first started looking at this with Dr. Marr, it was because of a program called DARPA ACT. The question was if the specs were actually achievable with classical digital approaches, and I happen to play in the space of non-classical digital and analog processing. The idea of ACT is to build a phased array system where the amount of bandwidth and number of beams that can be formed scales per unit Watt. This would allow powerful phased array technology to proliferate in many types of devices, not just expensive military radars. Also, the cloud computing revolution, in part, depends on Koomey's law continuing; if we are to cloud compute with mobile devices, we must be able to transmit, receive, and process wireless data for ever smaller energy levels assuming fixed or slowly growing energy density in batteries, which so far has been the case.

Conclusion: DARPA ACT will not hit their power target with classical digital approaches.
I have not yet seen the final reports, but I hope the teams prove me wrong. I doubt it.

Memory Power is stagnant?

Memory transfer power halves every 29 years, which makes memory power a fixed commodity calculation for data-flow systems. If you have data that is constantly changing, you are burdened by the speed and power of the data bus.

When it comes to memory, it really depends on architecture. As far as improvements, it's life in the slow lane.

What about measured performance in a non-dataflow system?

In a non-dataflow system, cache is king. If you cannot get data in faster, you need to keep it local and handy. I looked into what SPECInt2006 had to say about this using the Stanford CPUDB. If data transfer power is constrained by IO, you need have a lot of cache to minimize non-data instructions coming into the system, but what about power? Using the data in the CPUDB, I plotted SPECInt2006 basemean score per Watt, and then normalized it for processor cache.
I believe that these improvements in SPECint96 score are based upon increases in processor cache because the graph shows almost no trend when the cache is normalized across the processors. As data flow applications are not affected by substantial increase in cache sizes, I believe that there is little improvement between years due to scaling regarding score per Watt.
However, it does make a good argument for simpler code. When you consider that how large programs have gotten relative to cache, the Computer Science community should consider trimming the fat a bit.

Appendix

Of course, the data for the first figure, and the references.

yearnode(nm) processor GMAC/W ref





1980 3000 IBM PC-XT 0.000001 [19]





1980 3000 IBM PC 0.000002 [19]





1982 3000 commodore 64 0.000000 [20]





1984 3500 MACINTOSH 128K 0.000005 [2122]





1985 1500 IBM PC-AT 0.000002 [23]





1988 2000 MC68030 0.000017 [24]





1991 1000 INTEL 486 0.000065 [25]





1991 1000 IBM PS/2E 0.000086 [25]





1995 500 Pentium Pro 200 0.000182 [2627]





1992 750 DEC Alpha 21064 EV4 0.002632 [28]





1996 350 DEC Alpha 21264 EV6 0.001989 [2829]





1997 200 Early PowerPC 0.024056 [30]





1998 250 Pentium III 600B 0.003043 [31]





2001 180 PPC 7410 0.014720 [32]





2003 130 PPC 7447 0.017355 [33]





2003 130 Pentium 4 ee HT 3.2 0.006080 [34]





2003 130 TMS-320C6412-500 0.235215 [3536]





2003 90 TMS-320C6455-1000 0.210843 [37]





2004 90 POWER5 0.133000 [3839]





2006 65 Athlon X2 BE2300 0.029556 [40]





2006 65 Core 2 Extreme X6800 0.027375 [41]





2006 65 Core 2 QX6700 0.028711 [42]





2007 65 Pentium Dual-Core E2140 0.017231 [43]





2007 90 Monarch 0.746592 [4445]





2007 65 IBM Cell 0.248889 [46]





2007 90 PPC 8641D 0.027364 [47]





2007 90 TMS-320C6424-700 0.341988 [48]





2007 65 POWER6 0.063000 [3949]





2008 45 Core 2 T9400 0.050660 [5051]





2008 45 Atom 230 0.140000 [52]





2008 65 TMS-320C6474-850 0.153879 [53]





2008 65 TMS-320C6474-1000 0.166667 [53]





2008 65 TMS-320C6474-1200 0.193846 [53]





2008 40 Tesla C2050 0.757647 [5455]





2008 40 Tesla C2075 0.838698 [54]





2008 40 Tesla M2050 0.801422 [54]





2008 40 Tesla M2070 0.801422 [54]





2008 40 Tesla M2090 1.035378 [5456]





2008 45 Core i7-965 ee 0.034462 [57]





2009 65 TMS-320C6748 1.360703 [58]





2008 45 Atom N270 0.224000 [59]





2009 90 Tile64 0.712727 [60]





2009 40 ARM Cortex-A 1.085000 [61]





2010 NA Qualcomm Snapdragon 0.234500 [62]





2010 NA Tegra 3 0.101500 [62]





2010 45 POWER7 0.112000 [3963]





2010 40 Virtex 6 4.736630 [64]





2010 32 Core i7 980 ee 0.107682 [65]





2010 40 Fermi GTX480 0.941472 [54]





2011 40 Fermi GTX580 0.566977 [5466]





2011 40 SPARC T4 0.069953 [67]





2012 40 Virtex 7 7.269231 [64]





2012 28 Fermi GTX680 2.773465 [5468]





2012 32 Atom D2550 0.130200 [69]





2013 22 POWER8 0.168000 [3970]





2013 22 SPARC T5 0.168000 [71]





2013 22 Core i7-4960X 0.116308 [72]





2013 40 TMS320C6678-1250 0.823529 [73]





2013 28 R9 290x 3.942400 [74]





2013 28 Fermi GTX780 3.528000 [75]





2013 40 TILE-Gx72 0.806400 [76]





2014 28 Titan Black 3.584448 [77]





2014 22 E3-1284LV3 0.190638 [4]





2015 14 Kintex Ultrascale 4.806519 [64]





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