Gate Equivalents (GE) and why you should not use them.

I was introduced to Gate Equivalents (GEs) from using Xilinx layout tools, where the routed graph estimates how many NAND gates would be required for an implementation of a circuit. I keep reading papers were people use GEs as a comparison between designs, but it seems that the GE does not seem to have a standard definition. In many cryptography papers, the GE is used as an area comparison; however, this can be misleading. Let's say that you have a standard cell library with a large NAND gate, which is one GE. Now let's say that you have an XOR that is heavily optimized for area, and in this case, the XOR could have the same area of a NAND gate even though it requires more transistors.

Here is how people seem to game the system when GE is used as area. I make a NAND that is very large. This makes my total design take much less area in GEs for the other optimized cells. I just saw a design on 130nm that has fewer transistors with a higher GE than a design that has more transistors and a lower GE.

Instead of GEs, use transistor count. This just make sense. Here's an example of the layout of 8 transistors in a commercially available 14nm process:

This layout is substantially different from a 130nm equivalent. The attempt to compare different layouts and feature sizes with GEs is just worthless. Just don't do it.