Brief: On the design of solid state hard drives

The Solid State Drive (SSD) is a non-volatile storage device that shares a similar function to a traditional hard drive; however, the SSD architecture relies on a FLASH-type storage over a magnetic storage. This note is an executive summary of SSD architecture and throughput.

Introduction

The Solid State Drive (SSD) is a semiconductor-based replacement for the traditional hard drive. The traditional hard drive is bounded by a physical medium of spinning magnetic platters, and this is an example of physically constrained system. As an example, the hard drive is limited by the speed of the platters, the bounds on the head movement and the track width. The SSD is an electrically constrained system and examples of these limits the oxide thickness of a floating- gate transistor, and number of write cycles. SSDs mirror the functionality of hard drives.

Fig. 1. The illustration shows the basic architecture of a SSD. The major components are the cache, controller and FLASH storage. The major routes of communication are by the IO bus, the cache bus and the FLASH bus. The IO bus is connected between a computer interface and the controller, where the purpose of the controller is to mimic the behavior of a storage device and control the writes and reads. The controller also schedules writes between the DRAM cache and FLASH.

The SSD device

The SSD is a device that mimics the traditional hard drive in behavior, but uses solid-state semiconductor components instead of a mechanical medium. The SSD as a system is illustrated in Figure 1, and the device contains a controller and two types of storage, volatile and non-volatile. The purpose of the controller is to mimic the behavior of a hard drive and control writes. The non-volatile storage is the FLASH transistors from where solid state drives get their name. The volatile storage is a cache for temporary storage of data.

Table. 1. Different interface speeds.

Bounding SSD Performance

The SSD is created from several NAND FLASH ICs. As an individual device, the NAND FLASH perform differently be- tween generations; however, this performance can be masked by use of DRAM cache. The NAND in “NAND FLASH” refers to the addressing architecture and the FLASH term refers to the charge storage technique. The threshold of the FLASH MOSFET will shift depending on the charge that is trapped on the gate. The NAND FLASH is arranged in pages and reading and writing is based on this granularity [1]–[3]. Due to the abstraction away from the FLASH performance due to the DRAM cache, the write time of a packaged device is more of an academic exercise, and each 8k bank completes a write in 0.33ms to 0.45ms. The difference in these numbers is the difference between 50MB/sec and 33MB/sec; however, this is also abstracted away by local cache on the FLASH ICs, and possibly the controller. The slower write speed is preferred for endurance. [4], [5]. The bus speed of these devices will remain at approximately 20ns (50MHz) with current interconnect technologies with writes on the order of 200us and “erasing” on the order of 2ms. Bank reads are limited by IO, and thereby are bus limited. Due to the thin oxide and the tunneling process, even if the density of the devices increases, I do not believe that the speed of writing or erasing will increase due to the physics of quantum transport. The only increases that will be seen is interconnect and concurrent writes.

References

[1] A. Goda and K. Parat, “Scaling directions for 2d and 3d nand cells,” in 2012 International Electron Devices Meeting, 2012.
[2] H.-T. Lue, P.-Y. Du, W.-C. Chen, T.-H. Yeh, K.-P. Chang, Y.-H. Hsiao, Y.-H. Shih, C.-H. Hung, and C.-Y. Lu, “A novel dual-channel 3d nand flash featuring both n-channel and p-channel nand characteristics for bit- alterable flash memory and a new opportunity in sensing the stored charge in the wl space,” in 2013 IEEE International Electron Devices Meeting. IEEE, 2013, pp. 3–7. 2
[3] S.-H. Chen, H.-T. Lue, Y.-H. Shih, C.-F. Chen, T.-H. Hsu, Y.-R. Chen, Y.- H. Hsiao, S.-C. Huang, K.-P. Chang, C.-C. Hsieh et al., “A highly scalable 8-layer vertical gate 3d nand with split-page bit line layout and efficient binary-sum milc (minimal incremental layer cost) staircase contacts,” in Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012, pp. 2–3.
[4] K.-T. Park, S. Nam, D. Kim, P. Kwak, D. Lee, Y.-H. Choi, M.-H. Choi, D.-H. Kwak, D.-H. Kim, M.-S. Kim et al., “Three-dimensional 128 gb mlc vertical nand flash memory with 24-wl stacked layers and 50 mb/s high-speed programming,” IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 204–213, 2015.
[5] W. Kim, J. Y. Seo, Y. Kim, S. H. Park, S. H. Lee, M. H. Baek, J.-H. Lee, and B.-G. Park, “Channel-stacked nand flash memory with layer selection by multi-level operation (lsm),” in 2013 IEEE International Electron Devices Meeting. IEEE, 2013, pp. 3–8.