Previously, I mentioned that I was having issues with resistor extraction mismatch. I had some success that ended suddenly, and it forced me to carefully look at the kit. You need to preprocess your netlists in the schematic. The kit uses the file "cdl_processor.pl" to convert the extraction from the schematic.
The LVS release notes:
Hierachical LVS has requirements for CDL netlist inputs which require changes in the standard output
of CDL. Because of these requirements, a CDL processing program is included within the IBM
design kit.
In your schematic:
IBM_PDK->Netlist->CDL
IBM_PDK->Netlist->CDL Processor for LVS
This creates a file called (schematic).netlist.lvs.
In Calibre LVS (nmLVS) under Inputs, selected the "Netlist" tab and uncheck "export from schematic viewer" and specify the spice file as (schematic).netlist.lvs
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