IBM 130nm notes on LVS.

Back in 2007-ish, I helped teach a VLSI class at Georgia Tech that used IBM, now Global Foundaries, 130nm design kit. My academic webpages are long gone, but there are still scans of printouts of this old webpage and I get more questions about it from people all over the world. For that reason, here's most of the original document. I don't have the HSPICE lab description document that I wrote that this document references.

Okay, this is the quick and dirty overview of how to do IBM layout. There are some new tools and some new quirks, and this will cover DRC and LVC with Assura. The first thing which you should is copy my layers file to your working directory. Check out the ~degs/ece6130/ directory.

cp ~degs/ece6130/IBM.layers.degs ./_your_IBM_directory_

This will give you a managable subset of layers. Next, start up the kit as specificed in the HSPICE lab.

Adding the example library

I have made a test project, so you should first add it. From the "Library Manager" window, click on Edit->Library Path. You should get a dialog thta gives and edit lock error.

As multiple people can be working on the same project, Cadence only allows one person to edit things at a time regarding the libraries. You next need to get an exclusive lock.

Now that you have an exclusive lock, you can add my sample project to your library. The project is called "ex_assura".

~degs/ece6130

The above directory is where you should look for the ex_assura project.

After you add the direcotry, you should see it in the list.

You can then go to File->Save and save the new library path. You may then close the dialog.

Examining the example cell

You should see that in the "assura_ex" library, you have several cells. We will be introducing a few new layers to you, as well, how to manage the layers. There is a layer called "align" which you may use to put an alignment box around your cells which makes it easy to align them with respect to other cells. In the IBM toolkit, the "align" layer is white filled by default, which is annoying. Open up the layout for the NAND, and you should see the following image. I'll get to the big, horking white box in a moment.

In order to make this usable, we will introduce you to layer management, which is stored locally stored in the display.drf file in your startup directory. As should see in your layer map has more layers than you'd ever use. You might want to go to your layers window, and click on "Edit->Load", and then load the layers file which you copied in the begining of this tutorial. That will remove most of the layers which you won't be using.
note: you'll want to add and remove layers depending on your design decisions.
You can add and remove layers from the layers palette by going to the layers window and selecting "Edit->Set Valid Layers". The layers with "dg" next to them are the drawing layers. Generally, you'll need "dg" and "nt". You should go down the list and find the "align" layer and make sure that "dg" is set. The layer can be present on your screen, but you cannot select it unless you have it in your palette window!

Once you have found "align", you can then save the layers file. From here, you need to go to "Edit->Display Resource Editor" in the palette window. You can then change the fill style of the align layer. After you change the style, hit "apply" to update the information. You must then save in order to update the "display.drf" file which hold the layer information.

After you have saved your new display file, as soon as you update the layout window (pushing "f" for instance), you'll see that the align layer is no longer filed and it's just a white outline.

You have just learned how to leverage the display manager.

Layout

Gravity. Gravity is the reason that when you first open up the cell, that things are funny with your cursor. You need to turn it off if you want your pointer to actually go where you say for it to go. In the Virtuoso® (yeah, don't you love using software which reminds you that they've registered their quirks) layout window, go to "Options->Layout Editor" and then turn off "Gravity"; furthermore, I'd set the types to "none" as things don't always seem to obey without it.

Now that you have no gravity, and the layers aren't funny, you are set to go.
So, here's the introduction to new things. The new things live in the PDK->misc menu. The two options which you will use the most often are the "substrate contact based on RX" which is called "subc". This contact is your p-well tie down. The other contact is the "nwell contact based on RX", which is your nwell contact. As this a mixed mode process (analog is where the money is), there are some things which you need to do make things behave digitally. If you push "q" to bring up the properties window, and click around on the layers, you will notice a layer called "grlogic". The grlogic layer turns an analog process into something which goes by digital rules. For instance, if you are in "analog mode", subc is extracted and must be in your schematic. There is a cell called "NAND_analog" which you should open to see the differences in the schematics for identical layout.

We will assume that you can just look at what I've done, and then look at the example to get you started on your way to making your own cells. Assura is a good tool for DRC and LVS. It's slow for 10 transistors, but fast for 100000 when compared to DIVA DRC which you learned how to use the other labs. As usual, all of the magic happens from the PDK menu. You can feel free to try everything in that menu. "IBM_PDK->Checking" is where all of the checking tools live. I have made a broken cell for you already called "NAND_drcerror", you should open that cell up, and run DRC. Go to "IBM_PDK->Assura->DRC" to run DRC.

You will be asked if you want to overwrite old data possibly. The answer is yes, unless you and your partner are working out of the same account. If you are, you should change your "Run Directory" so that you don't step on each others toes. You probably want to make a run directory anyway so you don't have 1000 files in your project root. It will take a moment to fire up and you'll eventually get the following screen. You can either select what you want to look at, and then the update the layout window (via pressing "f" for example) to see the highlighted shapes. Alternatively, you can just hit "AV" for all view and then update the layout window to see everything highlighted at once. For specific errors, click on "View->Explain" and select which neon box of interest and a window will pop up which gives details about the error. Also, you may ignore any output which starts with: #INFO, it's only information.

On to LVS, I have made a cell called "NAND4_lvserror". This cell does not follow best-practices and if I find this in your turn-ins, you'll get what's coming to you because Mooney knows rubbish when he sees it; however, it's good to demonstrate LVS. Use the "IBM_PDK->Checking->Assura->LVS (VLDB) to start LVS.

Important things to do in this window.
As I mentioned before, this is an analog process, so in order to get the digital-style circuits during the extraction, you need to go to "Set Switches" and select "NO_SUBC_IN_GRLOGIC" to change the behavior of the extraction for parts inside the GRLOGIC layer. Also, for the "Run Directory", you should change it. You can see how I've setup things in the following image. Hit "Apply" and LVS will start. If you get an error, and it dumps you to the log file, start at the end of the file and look for the answer. The errors are very, very descriptive and they tell you how to fix the problem in 96% of the cases. Try that first before running to the TA. 5 minutes of searching will save you hours of waiting.

The cell will have errors. The error are listed by type, and you can double-click on the classifcations to bring up the tool. Notice that it suggest what should be doen to fix the error.

Alternatively, you can go to "View->LVS Error Report (Current Cell)" to bring up the net list of errors, and then you can select the names to highlight the mismatches on both the schematics and layout.

The cell updated to have no LVS errors is "NAND4". These examples should get you started down the right path. Thinks small first. Also, if you happen to use DIVA DRC (because someone will), you should note that you delete the markers by going to "Verify->Markers->Delete All" in the layout window.