package management when you don't have root.

Sometimes, you don't have root. The bsd-style ports tree let's you do this.

https://github.com/bpdegnan/redbash is a project that I have been using to install my bsd-style tools on commerical systems.

Primewave can execute a script before the command runs.

I just found that Primewave can execute a script before the simulator runs. In the Setup->Simulator panel, there's a "command prefix" field that will execute a script on the command line.

using ngspice with the skywater pdk.

shout the last goodbye I have a terrible time getting ngspice-43 working with skywater 130. There's some weird stuff in the PDK models, as it definitely is still the "IBM way". Firstly, you need to comment out any includes for any devices that aren't working in the sky130.lib.spice file. For me, it was all of the nfet_05v0_nvt devices.

* .include "../cells/nfet_05v0_nvt/sky130_fd_pr__nfet_05v0_nvt__tt.corner.spice"

The next issue is that "decks" have the devices have .models as a units of 1 meter. If you take a look at the sky130_fd_pr__nfet_01v8.pm3.spice file, you see how the subcircut (subckt) is generated.

.subckt  sky130_fd_pr__nfet_01v8 d g s b
+ 
.param  l = 1 w = 1 ad = 0 as = 0 pd = 0 ps = 0 nrd = 0 nrs = 0 sa = 0 sb = 0 sd = 0 mult = 1 nf = 1.0
msky130_fd_pr__nfet_01v8 d g s b sky130_fd_pr__nfet_01v8__model l = {l} w = {w} ad = {ad} as = {as} pd = {pd} ps = {ps} nrd = {nrd} nrs = {nrs} sa = {sa} sb = {sb} sd = {sd} nf = {nf}
.model sky130_fd_pr__nfet_01v8__model.0 nmos

This means that you need to create a .spiceinit file the same directory where you run the simulation. For me, I did this:

* .spiceinit for use with Skywater PDK and ngspice KLU
set ngbehavior=hsa     ; set compatibility for reading PDK libs
set skywaterpdk        ; skip some checks for faster lib loading
set ng_nomodcheck      ; don't check the model parameters
set num_threads=8      ; CPU processor cores available
option noinit          ; don't print operating point data
option klu             ; select KLU as matrix solver
optran 0 0 0 100p 2n 0 ; don't use dc operating point, but transient op%    

If you've gotten this far, this is how I did the whole thing. You need to install git, ngspice-43 and have some time download the 45GiB that is the skywater PDK.

git clone https://github.com/google/skywater-pdk.git
cd skywater-pdk
git checkout main
git submodule init
git submodule update

In the same directory as the .spiceinit file, I made this inverter.sp file:

* Inverter simulation using SkyWater 130nm PDK
.lib "$HOME/skywater-pdk/libraries/sky130_fd_pr/latest/models/sky130.lib.spice" tt
* Power supply
VDD VDD 0 1.8
* Input voltage source
VIN IN 0 PULSE(0 1.8 0 1n 1n 10n 20n)
* NMOS transistor
X1 OUT IN 0 0 sky130_fd_pr__nfet_01v8 
* PMOS transistor
X2 OUT IN VDD VDD sky130_fd_pr__pfet_01v8 
* Load capacitor
CL OUT 0 1p

.control
* Run transient analysis
tran 0.1n 50n
* plot v(IN) v(OUT)
* Save the results
wrdata inverter_simulation.raw v(IN) v(OUT)
.endc
.end

You will get some interesting warnings. This includes that a "scale" value is set somewhere to make the models based on nanometers, instead of meters. running "ngspice -b inverter.sp" yields:

degs@kazan inverter % ngspice -b inverter.sp
Warning: can't find the initialization file spinit.
Warning: Optran step size potentially too large.

Note: Compatibility modes selected: hs a

Warning: m=xx on .subckt line will override multiplier m hierarchy!


Circuit: * inverter simulation using skywater 130nm pdk

option SCALE: Scale is set to 1e-06 for instance and model parameters
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000

Using KLU as Direct Linear Solver
Note: Transient op started
Note: Transient op finished successfully
 Reference value :  0.00000e+00
No. of Data Rows : 535
Note: Simulation executed from .control section 

At this point, I used Python to read the raw file via "python plot.py inverter_simulation.raw" that is here:

import numpy as np
import matplotlib.pyplot as plt
import argparse

def read_and_plot(filename):
    # Load the data from the raw file
    data = np.loadtxt(filename)

    # Assuming the columns are:
    # Column 1: Time
    # Column 2: VIN
    # Column 3: Time again (redundant)
    # Column 4: VOUT

    time = data[:, 0]  # First column is time
    vin = data[:, 1]   # Second column is VIN
    vout = data[:, 3]  # Fourth column is VOUT

    # Plot the data
    plt.figure()
    plt.plot(time, vin, label='VIN')
    plt.plot(time, vout, label='VOUT')
    plt.xlabel('Time (s)')
    plt.ylabel('Voltage (V)')
    plt.title('Inverter Simulation')
    plt.legend()
    plt.grid(True)
    plt.show()

if __name__ == "__main__":
    parser = argparse.ArgumentParser(description='Plot ngspice simulation data.')
    parser.add_argument('filename', type=str, help='Path to the raw data file')
    args = parser.parse_args()

    read_and_plot(args.filename)

The results are wrong as I buggered up the netlist; however, it is actually functioning. This is a day that I will not get back. The bad graph is:

macports, building with all of the cores.

I noticed that I wasn't building on "all cores" with macports. The build.jobs addition to the command line makes it build... much faster.

port install inkscape build.jobs=8

pianobar with macports

I got stumped with default settings using pianobar (text-based Pandora client) under MacOS with macports. pianobar is highly configurable; however, something moved since I did this the last time and things did not work. it seems as if the name of the config file changed from pianobar.cfg to config.

mkdir -p ~/.config/pianobar
touch ~/.config/pianobar/config

You then can put your name and password in the file, such as

user = your@user.name
password = password

There are whole bunch of configurations for pianobar, and I sometimes tweak them.
One of the other things that you can do is remove your password explicitly from the config file. I use this:

password_command = gpg --decrypt ~/password

IBM 130nm notes on LVS.

Back in 2007-ish, I helped teach a VLSI class at Georgia Tech that used IBM, now Global Foundaries, 130nm design kit. My academic webpages are long gone, but there are still scans of printouts of this old webpage and I get more questions about it from people all over the world. For that reason, here's most of the original document. I don't have the HSPICE lab description document that I wrote that this document references.

Okay, this is the quick and dirty overview of how to do IBM layout. There are some new tools and some new quirks, and this will cover DRC and LVC with Assura. The first thing which you should is copy my layers file to your working directory. Check out the ~degs/ece6130/ directory.

cp ~degs/ece6130/IBM.layers.degs ./_your_IBM_directory_

This will give you a managable subset of layers. Next, start up the kit as specificed in the HSPICE lab.

Adding the example library

I have made a test project, so you should first add it. From the "Library Manager" window, click on Edit->Library Path. You should get a dialog thta gives and edit lock error.

As multiple people can be working on the same project, Cadence only allows one person to edit things at a time regarding the libraries. You next need to get an exclusive lock.

Now that you have an exclusive lock, you can add my sample project to your library. The project is called "ex_assura".

~degs/ece6130

The above directory is where you should look for the ex_assura project.

After you add the direcotry, you should see it in the list.

You can then go to File->Save and save the new library path. You may then close the dialog.

Examining the example cell

You should see that in the "assura_ex" library, you have several cells. We will be introducing a few new layers to you, as well, how to manage the layers. There is a layer called "align" which you may use to put an alignment box around your cells which makes it easy to align them with respect to other cells. In the IBM toolkit, the "align" layer is white filled by default, which is annoying. Open up the layout for the NAND, and you should see the following image. I'll get to the big, horking white box in a moment.

In order to make this usable, we will introduce you to layer management, which is stored locally stored in the display.drf file in your startup directory. As should see in your layer map has more layers than you'd ever use. You might want to go to your layers window, and click on "Edit->Load", and then load the layers file which you copied in the begining of this tutorial. That will remove most of the layers which you won't be using.
note: you'll want to add and remove layers depending on your design decisions.
You can add and remove layers from the layers palette by going to the layers window and selecting "Edit->Set Valid Layers". The layers with "dg" next to them are the drawing layers. Generally, you'll need "dg" and "nt". You should go down the list and find the "align" layer and make sure that "dg" is set. The layer can be present on your screen, but you cannot select it unless you have it in your palette window!

Once you have found "align", you can then save the layers file. From here, you need to go to "Edit->Display Resource Editor" in the palette window. You can then change the fill style of the align layer. After you change the style, hit "apply" to update the information. You must then save in order to update the "display.drf" file which hold the layer information.

After you have saved your new display file, as soon as you update the layout window (pushing "f" for instance), you'll see that the align layer is no longer filed and it's just a white outline.

You have just learned how to leverage the display manager.

Layout

Gravity. Gravity is the reason that when you first open up the cell, that things are funny with your cursor. You need to turn it off if you want your pointer to actually go where you say for it to go. In the Virtuoso® (yeah, don't you love using software which reminds you that they've registered their quirks) layout window, go to "Options->Layout Editor" and then turn off "Gravity"; furthermore, I'd set the types to "none" as things don't always seem to obey without it.

Now that you have no gravity, and the layers aren't funny, you are set to go.
So, here's the introduction to new things. The new things live in the PDK->misc menu. The two options which you will use the most often are the "substrate contact based on RX" which is called "subc". This contact is your p-well tie down. The other contact is the "nwell contact based on RX", which is your nwell contact. As this a mixed mode process (analog is where the money is), there are some things which you need to do make things behave digitally. If you push "q" to bring up the properties window, and click around on the layers, you will notice a layer called "grlogic". The grlogic layer turns an analog process into something which goes by digital rules. For instance, if you are in "analog mode", subc is extracted and must be in your schematic. There is a cell called "NAND_analog" which you should open to see the differences in the schematics for identical layout.

We will assume that you can just look at what I've done, and then look at the example to get you started on your way to making your own cells. Assura is a good tool for DRC and LVS. It's slow for 10 transistors, but fast for 100000 when compared to DIVA DRC which you learned how to use the other labs. As usual, all of the magic happens from the PDK menu. You can feel free to try everything in that menu. "IBM_PDK->Checking" is where all of the checking tools live. I have made a broken cell for you already called "NAND_drcerror", you should open that cell up, and run DRC. Go to "IBM_PDK->Assura->DRC" to run DRC.

You will be asked if you want to overwrite old data possibly. The answer is yes, unless you and your partner are working out of the same account. If you are, you should change your "Run Directory" so that you don't step on each others toes. You probably want to make a run directory anyway so you don't have 1000 files in your project root. It will take a moment to fire up and you'll eventually get the following screen. You can either select what you want to look at, and then the update the layout window (via pressing "f" for example) to see the highlighted shapes. Alternatively, you can just hit "AV" for all view and then update the layout window to see everything highlighted at once. For specific errors, click on "View->Explain" and select which neon box of interest and a window will pop up which gives details about the error. Also, you may ignore any output which starts with: #INFO, it's only information.

On to LVS, I have made a cell called "NAND4_lvserror". This cell does not follow best-practices and if I find this in your turn-ins, you'll get what's coming to you because Mooney knows rubbish when he sees it; however, it's good to demonstrate LVS. Use the "IBM_PDK->Checking->Assura->LVS (VLDB) to start LVS.

Important things to do in this window.
As I mentioned before, this is an analog process, so in order to get the digital-style circuits during the extraction, you need to go to "Set Switches" and select "NO_SUBC_IN_GRLOGIC" to change the behavior of the extraction for parts inside the GRLOGIC layer. Also, for the "Run Directory", you should change it. You can see how I've setup things in the following image. Hit "Apply" and LVS will start. If you get an error, and it dumps you to the log file, start at the end of the file and look for the answer. The errors are very, very descriptive and they tell you how to fix the problem in 96% of the cases. Try that first before running to the TA. 5 minutes of searching will save you hours of waiting.

The cell will have errors. The error are listed by type, and you can double-click on the classifcations to bring up the tool. Notice that it suggest what should be doen to fix the error.

Alternatively, you can go to "View->LVS Error Report (Current Cell)" to bring up the net list of errors, and then you can select the names to highlight the mismatches on both the schematics and layout.

The cell updated to have no LVS errors is "NAND4". These examples should get you started down the right path. Thinks small first. Also, if you happen to use DIVA DRC (because someone will), you should note that you delete the markers by going to "Verify->Markers->Delete All" in the layout window.